Intel prolongs Moore’s Law by introducing 3D packing technology, Foveros, which allows for stacking of more transistors and other components into chips

Briefing

Intel prolongs Moore’s Law by introducing 3D packing technology, Foveros, which allows for stacking of more transistors and other components into chips

January 4, 2019

Briefing

  • 3D Packing Technology – Intel demonstrated its new 3D packing technology called Foveros that allows chips to be layered on top of each other at Intel Architecture Day on December 11, 2018
  • New Method – Intel’s vertical solution can enable continuation of Moore’s Law, which posits that chips will continue to get smaller while packing more transistors
  • Vertical Solution – Can pack more transistors, as well as include more functionalities, such as 5G radio, central processing unit (CPU) and more, in given space
  • Prevents Heating – Solved heating problem that normally occurs when chips are stacked by inventing insulation material to dissipate heat, conducting more tests, and developing new power delivery process
  • Supporting Products – Consumer products using Foveros expected to launch in 2019

Accelerator

Sector

Information Technology

Organization

Intel Corp.

Source

Original Publication Date

December 12, 2018

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